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Altera_Forum's avatar
Altera_Forum
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10 years ago

[RapidIO] How to simulate RapidIO IP core？

Dears,

Based on RapidIO UG V14.0(Aug 2014), Page 26, Simulating the Testbench with the ModelSim Simulator, there are 5 steps to simulate the IP.

In step 3, need srio_simulator.tcl file, but I searched the whole directory of my project, can't find this tcl file. Only msim_setup.tcl exist in ..simulation\mentor when I generate the RapidIO IP core.

I have no idea how to simulate RapidIO IP core？ UG seems give us the wrong information.

version: QuartusII 15.0 Update 1

IP: RapidIO MegaCore Function

I really need your help, Thanks a lot!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    HI Chris,

    I've sent your post to TechDocFeedback@altera.com. A Technical Writer on Altera's staff will investigate the answer to your issue with the user guide, and I can post the response here. Alternately, you can write to the feedback email address to get a direct response. Note that a Send Feedback link appears on each page of newer Altera documentation which you can use for questions like these.

    Regards,

    Severin Foreman

    Manager, Technical Communications

    Altera Corporation
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    An Altera Technical Writer wrote the following response to your query. I hope it helps. For other issues related to technical documentation, please write to TechDocFeedback@altera.com, and we will send you a direct response.

    Regards,

    Severin Foreman

    Manager, Technical Communications

    --- Begin response ---

    The RapidIO MegaCore Function User Guide currently on the Altera website is correct for the 14.0 and 14.0 Arria 10 Edition software releases. However, it is out of date for the 14.1 and 15.0 releases, and some changes have occurred in the simulation instructions.

    These changes are partially explained in the known issue in the Altera Knowledge Base at https://www.altera.com/support/support-resources/knowledge-base/solutions/fb247103.html . Additional changes that will appear in the Knowledge Base in the next week or so are listed below:

    1. Listed already: TOP_LEVEL_NAME for ModelSim simulation of Arria 10 RapidIO IP core variations has changed in the 14.1 release, to <your_ip>_altera_rapidio_<version>.tb.

    2. To be added soon: TOP_LEVEL_NAME for ModelSim simulation of non-Arria 10 RapidIO IP core variations has changed in the 14.1 release, to rapidio_0.tb 3. To be added soon: Instructions that involve the srio_simulator.tcl file for simulation of non-Arria 10 RapidIO IP core variations are no longer valid, starting in the 14.1 release. You can simply skip the instructions in the 14.0/14.0 Arria 10 Edition user guide that ask you to type "do srio_simulator.tcl".