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Altera_Forum
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10 years ago

Ramb16_s1_s1

Hi to all

I'm tring to use a XILINX design but I don't manage to make a RAMB16_S1_S1 with megawizard.

This is the component :

--- Quote Start ---

component RAMB16_S1_S1 is

port (

CLKA : in std_logic;

ADDRA : in STD_LOGIC_VECTOR (13 downto 0);

DIA : in STD_LOGIC_VECTOR (0 downto 0);

DOA : out STD_LOGIC_VECTOR (0 downto 0);

ENA : in STD_LOGIC;

SSRA : in STD_LOGIC;

WEA : in STD_LOGIC;

CLKB : in std_logic;

ADDRB : in STD_LOGIC_VECTOR (13 downto 0);

DIB : in STD_LOGIC_VECTOR (0 downto 0);

DOB : out STD_LOGIC_VECTOR (0 downto 0);

ENB : in STD_LOGIC;

SSRB : in STD_LOGIC;

WEB : in STD_LOGIC

);

end component;

--- Quote End ---

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    You need to look for the 'RAM: 2-PORT' IP from the catalog.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks for your answer.

    I've already tried 'RAM: 2-PORT' but I don't know what is these signals :

    ENA : in STD_LOGIC;

    SSRA : in STD_LOGIC;

    WEA : in STD_LOGIC; (wren_a I think)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks for your help.

    I've tested this but not work. :confused: 

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity vdp_vram is
    port (
        cpu_clk:        in  STD_LOGIC;
        cpu_WE:        in  STD_LOGIC;
        cpu_A:        in  STD_LOGIC_VECTOR (13 downto 0);
        cpu_D_in:    in  STD_LOGIC_VECTOR (7 downto 0);
        cpu_D_out:    out STD_LOGIC_VECTOR (7 downto 0);
        vdp_clk:         in  STD_LOGIC;
        vdp_A:        in  STD_LOGIC_VECTOR (13 downto 0);
        vdp_D_out:    out STD_LOGIC_VECTOR (7 downto 0));
end vdp_vram;
architecture Behavioral of vdp_vram is
component RAMB16_S1_S1 is
    PORT
    (
        aclr_a        : IN STD_LOGIC  := '0';
        aclr_b        : IN STD_LOGIC  := '0';
        address_a        : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
        address_b        : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
        clock_a        : IN STD_LOGIC  := '1';
        clock_b        : IN STD_LOGIC ;
        data_a        : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
        data_b        : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
        enable_a        : IN STD_LOGIC  := '1';
        enable_b        : IN STD_LOGIC  := '1';
        wren_a        : IN STD_LOGIC  := '0';
        wren_b        : IN STD_LOGIC  := '0';
        q_a        : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
        q_b        : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
    );
end component;
begin
    ram_blocks:
    for b in 0 to 7 generate
    begin
        inst: RAMB16_S1_S1
        port map (
            clock_a    => cpu_clk,
            address_a    => cpu_A,
            data_a    => cpu_D_in(b downto b),
            q_a    => cpu_D_out(b downto b),
            enable_a    => '1',
            aclr_a    => '0',
            wren_a    => cpu_WE,
            clock_b    => not vdp_clk,
            address_b    => vdp_A,
            --data_b    => "0",
            data_b    => "0",
            q_b    => vdp_D_out(b downto b),
            enable_b    => '1',
            aclr_b    => '0',
            wren_b    => '1'
        );
    end generate;
end Behavioral;

    This is original file : 

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity vdp_vram is
    port (
        cpu_clk:        in  STD_LOGIC;
        cpu_WE:        in  STD_LOGIC;
        cpu_A:        in  STD_LOGIC_VECTOR (13 downto 0);
        cpu_D_in:    in  STD_LOGIC_VECTOR (7 downto 0);
        cpu_D_out:    out STD_LOGIC_VECTOR (7 downto 0);
        vdp_clk:         in  STD_LOGIC;
        vdp_A:        in  STD_LOGIC_VECTOR (13 downto 0);
        vdp_D_out:    out STD_LOGIC_VECTOR (7 downto 0));
end vdp_vram;
architecture Behavioral of vdp_vram is
begin
    ram_blocks:
    for b in 0 to 7 generate
    begin
        inst: RAMB16_S1_S1
        port map (
            CLKA    => cpu_clk,
            ADDRA    => cpu_A,
            DIA    => cpu_D_in(b downto b),
            DOA    => cpu_D_out(b downto b),
            ENA    => '1',
            SSRA    => '0',
            WEA    => cpu_WE,
            CLKB    => not vdp_clk,
            ADDRB    => vdp_A,
            DIB    => "0",
            DOB    => vdp_D_out(b downto b),
            ENB    => '1',
            SSRB    => '0',
            WEB    => '0'
        );
    end generate;
end Behavioral;