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Altera_Forum
Honored Contributor
Honored ContributorRamb16_s1_s1
Hi to all I'm tring to use a XILINX design but I don't manage to make a RAMB16_S1_S1 with megawizard. This is the component : --- Quote Start --- component RAMB16_S1_S1 is ...
Altera_ForumHonored Contributor
Honored ContributorEN(A) - enable
SSR(A) - synchronous set/reset WE(A) - write enable "A" refers to port A. Read "using block ram in spartan-3 generation fpgas (http://www.xilinx.com/support/documentation/application_notes/xapp463.pdf)". With Altera's 2-port RAM IP, you don't need the enable, 'wren' for WE and 'aclr' is available for SSR. Cheers, Alex
