Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Ramb16_s1_s1

Hi to all I'm tring to use a XILINX design but I don't manage to make a RAMB16_S1_S1 with megawizard. This is the component : --- Quote Start --- component RAMB16_S1_S1 is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thanks for your answer.

I've already tried 'RAM: 2-PORT' but I don't know what is these signals :

ENA : in STD_LOGIC;

SSRA : in STD_LOGIC;

WEA : in STD_LOGIC; (wren_a I think)