RAM initialization with .mif using logic elements?

I write a ram module with Intel's template. It is working fine amd not uses any logic elements without initializing it. But when I initialize it with a .mif file that I created, it uses logic elements which I don't want it because I lack of logic elements. Am I doing wrong with initialization or is this normal when we doing ram init. If it is, is there any way to store data without using logic elements?

library ieee;
use ieee.std_logic_1164.all;

entity dev_i2c_conf_ram is
	generic 
	(
		DATA_WIDTH : natural := 16;
		ADDR_WIDTH : natural := 298
	);

	port 
	(
		clk		: in std_logic;
		addr		: in natural range 0 to (ADDR_WIDTH - 1);
		data_in	: in std_logic_vector((DATA_WIDTH - 1) downto 0);
		we			: in std_logic;
		data_out	: out std_logic_vector((DATA_WIDTH - 1) downto 0)
	);
end entity;

architecture rtl of dev_i2c_conf_ram is

	-- Build a 2-D array type for the RAM
	subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
	type ram_t is array(((ADDR_WIDTH) - 1) downto 0) of word_t;

	-- Declare the RAM signal.	
	signal ram : ram_t;
	
	-- Initialize RAM
	attribute ram_init_file : string;
	attribute ram_init_file of ram :
	signal is "dev_i2c_conf.mif";
	
	-- Register to hold the address/page 
	signal addr_reg : natural range 0 to ((ADDR_WIDTH) - 1);

begin

	process(clk)
	begin
	if(rising_edge(clk)) then

		if(we = '1') then
			ram(addr) <= data_in;
		end if;

		-- Register the address for reading
		addr_reg <= addr;
	end if;
	end process;

	data_out <= ram(addr_reg);

end rtl;