Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorRadix adjustment
Hi,
is there a possiblity to give a fix radix representation to e.g. std_logic_vector like HEX for the simulation output in the testbench? Mel7 Replies
Altera_Forumyou can also add that wave.do to your main simulation .do or add the commands to the main simulation .do directly
- Altera_Forum
ok thanks!
- Altera_Forum
once you've made all the setup changes, you can save the wave window to a .do file, that saves all the radix's for all the signals, that can be reloaded when you restart modelsim.
- Altera_Forum
Yes, but I'm asking for a possiblity to make this setup already fix before simulation.... I don't if its possible
- Altera_Forum
I dont quite understand - a std_logic_vector is an array of std_logic, so the radix is just a display parameter, not part of the VHDL code.
- Altera_Forum
This I know, but I mean to set it fix for a certain output already in the testbench befor simulating it
- Altera_Forum
Yes in modelsim.
Right click on the signal in the wave window and select radix -> hex.
