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Altera_Forum's avatar
Altera_Forum
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14 years ago

Radix adjustment

Hi, is there a possiblity to give a fix radix representation to e.g. std_logic_vector like HEX for the simulation output in the testbench? Mel
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I dont quite understand - a std_logic_vector is an array of std_logic, so the radix is just a display parameter, not part of the VHDL code.