Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorRadix adjustment
Hi, is there a possiblity to give a fix radix representation to e.g. std_logic_vector like HEX for the simulation output in the testbench? Mel
Altera_ForumHonored Contributor
Honored ContributorThis I know, but I mean to set it fix for a certain output already in the testbench befor simulating it
