Quirk with my clocks

The problem you have may be creating "ripple clocks". These are bad. A ripple clock is where you use registers in your design to act as a new clock. What you should be creating instead are clock enables.

To create a clock enable structure try:

PROCESS(reset, clock)
BEGIN
    IF (reset = '1') THEN
        counter <= 0;
        clock_enable <= '0';
    ELSIF (rising_edge(clock)) THEN
        IF (counter = counter_limit - 1) THEN
            clock_enable <= '1';
            counter <= 0;
        ELSE
            clock_enable <= '0';
            counter <= counter + 1;
        END IF;
    END IF;
END PROCESS;

Aside from that, your code to generate the count down behavior should probably make use of a good synchronous reset. Building a process with an asynchronous reset and a clock enable looks like this:

PROCESS(reset, clock)
BEGIN
    IF (reset = '1') THEN
        --put initial conditions here
    ELSIF (rising_edge(clock)) THEN
        IF (clock_enable = '1') THEN
          --put code here
        END IF;
    END IF;
END PROCESS;