Quirk with my clocks

In that case all you need is to make sure your divided clocks are in phase. But to avoid the hassle I will run counter1sec on its clock starting from say 1000 at reset release. Then I will run counter10sec starting from say 100 after reset release on same clock but use the other 1/10 clock as clockenable to count down.

Thus at start after reset release it should align like this:

1000 999 998 997 996 995 994 993 992 991 990 ...

100 100 100 100 100 100 100 100 100 100 99 ...

and don't forget to keep clock enable under reset till release.