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Altera_Forum
Honored Contributor
Honored ContributorQuick VHDL question about splitting/joining std_logic_vectors
I have a memory block in my VHDL code and it has output std_logic_vectors that are 32 bit wide. I want to connect those to smaller std_logic_vectors and individual bits of std_logic in some cases.
Is there a quicker way of doing this than to assign them to a signal and then assign individual parts of that signal to my smaller signals using several lines of destination <= signal(31 downto 16) or similar?
WCONF: wheelconfig PORT MAP (
clk=>clk, addr=>addr(3 downto 0), -- Assign 4 lowest bits of global address bus
wren=>wc_wr,
data_in=>data_in,
data_out=>wheelconfig_read
data0=> -- Here lets say I have a vector of 16 bits, a vector of 8 bits, a vector of 4 bits and 4 invidual bits to assign.
);
3 Replies
Altera_ForumYes, I'm well aware that there are no overheads involved, this was simply a readability issue. The aliases seem to be exactly what I need. Thank you.
- Altera_Forum
data => data1 & data2 & data3 & data4
is a bit shorter kaz - Altera_Forum--- Quote Start --- Is there a quicker way of doing this --- Quote End --- The only slow thing is, that you have to write a few lines of code. In the sythesized logic, the signals are connected directly. Thus I regard it's the most effective way, usually. To improve readability of your code, ALIAS definitions may be in appropriate way. They are, however limited to a signal type. If the original signal is std_logic_vector, the partial alias expressions have to be std_logic_vector or std_logic. In individual assignments, you are free to cast to a different type, e.g. signed or unsigned.
Another way is in defining structured data types, which are generally supported by VHDL.SIGNAL controlreg : STD_LOGIC_VECTOR (15 downto 0); ALIAS TriggerMode : STD_LOGIC_VECTOR (2 downto 0) IS controlreg(2 downto 0); ALIAS TrgMode_nSPI : STD_LOGIC IS controlreg(0); ALIAS TrgMode_WCtrl : STD_LOGIC IS controlreg(1); ALIAS TrgMode_WStat : STD_LOGIC IS controlreg(2);
