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Is there a quicker way of doing this
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The only
slow thing is, that you have to write a few lines of code. In the sythesized logic, the signals are connected directly. Thus I regard it's the most effective way, usually.
To improve readability of your code, ALIAS definitions may be in appropriate way. They are, however limited to a signal type. If the original signal is std_logic_vector, the partial alias expressions have to be std_logic_vector or std_logic. In individual assignments, you are free to cast to a different type, e.g. signed or unsigned.
SIGNAL controlreg : STD_LOGIC_VECTOR (15 downto 0);
ALIAS TriggerMode : STD_LOGIC_VECTOR (2 downto 0) IS controlreg(2 downto 0);
ALIAS TrgMode_nSPI : STD_LOGIC IS controlreg(0);
ALIAS TrgMode_WCtrl : STD_LOGIC IS controlreg(1);
ALIAS TrgMode_WStat : STD_LOGIC IS controlreg(2);
Another way is in defining structured data types, which are generally supported by VHDL.
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