Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Quick VHDL question about splitting/joining std_logic_vectors

I have a memory block in my VHDL code and it has output std_logic_vectors that are 32 bit wide. I want to connect those to smaller std_logic_vectors and individual bits of std_logic in some cases. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Yes, I'm well aware that there are no overheads involved, this was simply a readability issue. The aliases seem to be exactly what I need. Thank you.