questions about parameter define

verilog code:

parameter A_BIT = 4'd9;

parameter B_BIT = 4'd12;

output [A_BIT+ B_BIT -1 :0] sig_tmp;

After synthesize, sig_tmp is 5 bit.

I know "parameter A_BIT = 4'd9" should be "parameter A_BIT = 9", and also B_bit.

I want to know why the result of "A_BIT+ B_BIT" in "[A_BIT+ B_BIT -1 :0]" is still 4bit , but not 5 bit.

Thank you.