Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Question on LE

Dear all, Im wondering if it is possible to have a design that actually has fewer logic gates but took up more LE than another design that has more logic gates? This is happened to my desi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Your definition of "gates" is rather arbitrary, I think. Can you actually assume XOR as one "gate"? It's build of multiple low level gates internally. But FPGAs don't have the kind of gates you imagine.