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Altera_Forum
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16 years ago

Question on LE

Dear all, Im wondering if it is possible to have a design that actually has fewer logic gates but took up more LE than another design that has more logic gates? This is happened to my desi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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in that case, can I unable the optimization in the synthesis tool ?

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Hi,

why do want to disable the optimization ? How many gates do you have in your design ?

Kind regards

GPK