Question on implementation of a SERDES CycloneIII LVDS Interface

Dear all,

we am currently designing a readout and data transmission board that will be instrumented with a Cyclone III EP3C80F780C7N and I would like to request your opinion on the configuration of a DDR LVDS SERDES bus.

We plan to use the True LVDS banks of the EP3C80F780C7N (1, 2, 5 and 6) to connect to two National DS32EL0421SQ Serializers and two DS32EL0124SQ Deserializers. Each chip is connected to a single True LVDS bank in order to have a straight routing from the outer edges LVDS pins with minimum skew, avoiding the need to use vias. The SERDES chips are placed close to the FPGA so that the routing length is no larger than 2-3 cm.The SERDES use a 5-bit DDR LVDS parallel data interface with a differential LVDS clock from 125 MHz to 312.5 MHz.

We will be using for the deserializers reception banks 1 and 5, with the output clock from the deserializers driving DIFFCLK_0p/n and DIFFCLK_3p/n PLL inputs, respectively. Since banks 3, 4, 7 and 8 are banks with VCCIO at 1V5 and 3V3 I am not using the PLL dedicated outputs on these banks to drive the serializers. Instead we intend to feed an external differential 80 MHz clock, generated by an differential oscillator, in the DIFFCLK_1p/n and DIFFCLK_2p/n PLL inputs of banks 2 and 6 and extracting the serializers driving clock on a general I/O LVDS pair from the True LVDS banks 2 and 6. Although the output clock is being taken out from a general LVDS IO pair, in this way I can get a very "clean" routing to the serializer/deserializer chips, minimizing the skew between clock and data outputs although perhaps at the expense of an additional jitter from not using the dedicated PLL outputs.

Do you think this approach can work and what are other possible design options that could be used to make the design more resilient? We are going to implement this approach on Quartus II, using the ALTLVDS, but I would be appreciated for any comments or suggestions.

Best,

Pedro