Altera_ForumHonored Contributor14 years agoQuestion of Cyclone3 and DDR2 I use BANK 3、4 and BANK5、6 of EP3C16F484 in controlling 64Bit DDR2 , can I use the Unused IO PINs of these banks as the input for 1.8V LVTTL signal ? thanks.
Recent DiscussionsCyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memoryWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File Information