Altera_ForumHonored Contributor14 years agoQuestion of Cyclone3 and DDR2 I use BANK 3、4 and BANK5、6 of EP3C16F484 in controlling 64Bit DDR2 , can I use the Unused IO PINs of these banks as the input for 1.8V LVTTL signal ? thanks.
Recent DiscussionsPower-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) DevicesRegarding Power-Up Sequence for Agilex 5Cyclone V SoC 5CSXC6 Series GXB Utilization and LimitationsHow to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?Agilex 3 PLL in Source Synchronous mode ?