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Honored Contributor
Honored ContributorQuestion about warning in Quartus II
I have done FPGA and CPLD design before, but i have never seen this error and am not sure if it is something i need to worry about or if it is a setting i need to change...im sure someone can tell me quickly.
Warning: Ignored locations or region assignments to the following nodes Warning: Node "TCK" is assigned to location or region, but does not exist in design Warning: Node "TDI" is assigned to location or region, but does not exist in design Warning: Node "TDO" is assigned to location or region, but does not exist in design Warning: Node "TMS" is assigned to location or region, but does not exist in design Obviously, these are the JTAG signals, i assigned them in the pin planner, which is all i thought i would have to do. Is there something else i need to set in the software to get rid of these warnings? Thanks, Dan5 Replies
Altera_Forum--- Quote Start --- many thanks i cant seem to remove the pin assignment, but i will know the warning is meaningless. :) --- Quote End --- You can always just delete the assignments from the QSF file using any test editor.- Altera_Forum
many thanks
i cant seem to remove the pin assignment, but i will know the warning is meaningless. :) - Altera_Forum
You don't need. The reason is simple; they are not used in your design modules to drive or be driven. They are meant for internal JTAG circuitry and altera knows them and already connected them internally.
- Altera_Forum
they are wired in hardware, are you saying i dont need to assign them on the pin planner?
- Altera_Forum
You don't need to assign these dedicated pins. You need to wire them in hardware but not in vhdl
