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Altera_Forum
Honored Contributor
Honored ContributorQuestion about warning in Quartus II
I have done FPGA and CPLD design before, but i have never seen this error and am not sure if it is something i need to worry about or if it is a setting i need to change...im sure someone can tell me...
Altera_ForumHonored Contributor
Honored Contributormany thanks
i cant seem to remove the pin assignment, but i will know the warning is meaningless. :)
