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Altera_Forum's avatar
Altera_Forum
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15 years ago

Question about warning in Quartus II

I have done FPGA and CPLD design before, but i have never seen this error and am not sure if it is something i need to worry about or if it is a setting i need to change...im sure someone can tell me...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

they are wired in hardware, are you saying i dont need to assign them on the pin planner?