Honored ContributorHi, I am reading the PCIE compiler guide, and trying to build my design using the the PCIE IP.
https://www.alteraforum.com/forum/attachment.php?attachmentid=6710 The above diagram is the reference design in this document. My question is what is the bus functional model? How is module simulate the PCIE IP? Is the Root port driver simulate the device driver in PC? Thanks for your input
Honored ContributorThe Root Port BFM (bus functional model) is used to provide stimulus to the PCIe IP. PCIe is very complicated, so you have to have something that creates data correctly or the PCIe IP core won't even begin to work. The BFM simulates the PC hardware and driver. It's not an exact match because different PCs act a bit differently and so do drivers.
Honored ContributorHi,
Could you provide any input to simulate PCIe as Root Port? My Quartus is 12.1Honored Contributorde_prince,
If your design is a PCIe root port (not an end point), you'll need a BFM that acts as an endpoint. Other than what Altera has, I'm not aware of any low cost BFMs to do that. If your design is an endpoint, then you need a root port BFM to drive it, and both Altera's BFM and DrivExpress should work for simulation. You might find other product out there, too, but those are the two I'm aware of.
