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Altera_Forum
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13 years ago

Question about root port bus functional model

Hi, I am reading the PCIE compiler guide, and trying to build my design using the the PCIE IP. https://www.alteraforum.com/forum/attachment.php?attachmentid=6710 The above diagram is the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi,

Could you provide any input to simulate PCIe as Root Port? My Quartus is 12.1