Question about Monitor

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Can I assign virtual pins to bidirectional pins.

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Why would you want to? If they are attached to physical pins, they will not get removed by synthesis.

Cheers,

Dave

Hello Dave,

Can I assign virtual pins to bidirectional pins. I am getting a Critical Warning "No exact pin location assignment(s) for 37 pins of 43 pins". In my .qsf file I have assigned all of these pins as virtual pins [and all these pins are Bidirectional].

Thanks and enjoy the weekend

Aditya

Hi Aditya,

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Is there a way to switch of the "Trimming" in Quartus. The software automatically trims all pins that does not have a fan out. Can I tell the software not to do this. I tried setting the pins to virtual pins but it did not help. [Also, I could not get all the pins listed].

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I'm not sure what you are talking about. Could you provide an example of pins that you would like to keep that are getting removed.

Perhaps the synthesis 'keep' directive is what you need?

http://quartushelp.altera.com/11.0/master.htm#mergedprojects/hdl/vlog/vlog_file_dir_keep.htm

http://quartushelp.altera.com/11.0/master.htm#mergedprojects/hdl/vhdl/vhdl_file_dir_keep.htm

Cheers,

Dave

Good Morning Dave,

Thanks!. Is there a way to switch of the "Trimming" in Quartus. The software automatically trims all pins that does not have a fan out. Can I tell the software not to do this. I tried setting the pins to virtual pins but it did not help. [Also, I could not get all the pins listed].

Thanks,

Aditya

Hi Aditya,

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I have a master BFM connected to the slave port of the PCIe core [core one]. This core is connected to the master target memory. Can I write data to the target memory using API calls to the master BFM.

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Where is this memory again? In the testbench PCIe master, or in the PCIe slave device? Either way, your Avalon-MM BFM in the master should be able to write to it. Eg., if the RAM is in the testbench PCIe master, then the Avalon-MM BFM can simply write to the address of the RAM. However, if the RAM is in the PCIe slave device, then the Avalon-BFM master in the PCIe master core first has to setup the PCIe master and then the PCIe slave interfaces.

PCIe traffic generally undergoes an address translation, and these are the registers you need to setup. For example, lets say the address map of your PCIe master design has an address decode to generate bus transactions setup at Avalon-MM address 0x1000_0000 in the master design. Any access by the Avalon-MM BFM master in the first design to this address will generate traffic on the PCIe bus. The packet that gets transmitted on the PCIe bus may have the same address, or it may have a translated address, lets say it gets translated to 0x2000_0000. If the PCIe slave has a BAR setup to respond to accesses to PCIe address 0x2000_0000, then it will accept that address. The PCIe slave may then implement address translation, eg. lets say it converts the MSBs of the address so that the translated addresses start at 0x3000_0000. The PCIe slave will then initiate an Avalon-MM transaction at address 0x3000_0000 in the slave device memory map. If the slave RAM is located at that address, then your Avalon-MM master back in the first design will successfully access the RAM in the second design.

The key thing to understand is the address mapping.

Cheers,

Dave

(Note: I assume this is how it works for PCIe, as this is how things work for PCI).

Good Morning Dave,

I have a master BFM connected to the slave port of the PCIe core [core one]. This core is connected to the master target memory. Can I write data to the target memory using API calls to the master BFM.[ through this call I want to control the core one. And using core one I want to control the target ]. Similar to PCIe BFM design you sent me

Thanks.

Aditya

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What you have told sounds exciting!! How do I measure the power dissipated on the board?

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If you have a board with current sensors, then you read the current sensors :)

If you don't then you can do it this way;

1) Power your board from a supply that you can measure the current, eg., replace a 12V wall-wart with a bench-top power supply, or cut the wires and put an ammeter in series with the supply wire.

2) Download a design that uses 'some' power, and measure the current when its operating.

3) Download another design that uses 'more' power, and measure the current when its operating.

4) See if the difference between the power measured in (3) and (2) is equivalent to the different predicted by Altera's tool.

Note that before you compare currents, you will have to translate your Quartus predicted FPGA supply rail currents into input power supply load current. To do this, you'll have to look at the power supply design and see whether the power supplies are linear (the input current is the same as the FPGA rail current) or switch-mode (the input current is less than the FPGA rail current by the ratio of voltages and efficiency, eg. 1.2A@1A = 12V@ 1Ax1.2V/12V/0.85 = [email protected] for 85% conversion efficiency).

Cheers,

Dave

Hello Dave,

What you have told sounds exciting!! How do I measure the power dissipated on the board?

Thanks,

Aditya

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My main objective is to explore the software, I thought of getting into hardware simulations later. Can you give me few other designs / guide me to a reference book that has reference designs.

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The best way to learn is to complete an entire project, including the hardware.

For example, lets say you have an evaluation board, and that board has PCIe and DDR3 memory, and perhaps some SRAM and Flash. You could generate an SOPC (or Qsys) system for those components, and then make sure it meets timing. From the timing analysis, determine what the maximum frequency you can get the design to work at. How much power should that design be dissipating; what does PowerPlay estimate, use Modelsim to generate a .vcd file, and then run that through PowerPlay too.

Then test everything in hardware to make sure it works.

Measure the power; compare it to PowerPlay's estimates.

Try over-clocking the design to see where it fails (this is hard to do in some designs, eg., you might not be able to overclock the PCIe bus, but you could try overclocking your DDR). Even if Quartus indicates you've failed timing for say the DDR interface, go and test it in hardware; is Quartus being conservative? Spray quickfreeze or a heatgun on a design and see if it continues to work. How can you tell if a design is 'working'? Well, if you have a DDR interface, generate lots of single/burst read/write traffic that is automatically checked, eg. a PRBS generator to create data, a controller that generates single and/or burst writes to memory, and then another to generate single and/or burst reads to the memory, and a checker to check the values read from memory. Have the checker count the read failures and then your control software can read them back and display them, so you can see if your quickfreeze spray or heatgun is affecting the design.

Add a NIOS II embedded processor to the system. Write some code for it. If you plugged the card into a PCIe bus, how would you communicate with that NIOS II processor? Its not as simple as plugging in an ethernet or serial cable, since you want a direct link via the PCIe bus. Can you make it look like a serial port or ethernet link? Can you communicate with the board from Windows over PCIe, how about Linux?

There's lots of things you can do to learn 'the software', just keep in mind that the software is not just the Quartus tool, its the entire suite of tools, and then Windows or Linux device driver and application tools.

If you want to become a good engineer, learn about all of the tools needed to construct a system, not just one tool for one piece of a system.

Cheers,

Dave

Hello Dave,

My main objective is to explore the software, I thought of getting into hardware simulations later. Can you give me few other designs / guide me to a reference book that has reference designs.

Thanks,

Aditya