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Have you actually designed this component as an SOPC Component? i.e., does it have an Avalon-MM slave interface to write the values and then enable the calculation of the five largest values.
What is the point of this algorithm?
How many bits do each value have? Where do these samples come from?
Rather than calculate the five highest values, I think keeping the five highest values are you write would be more efficient, i.e., the Avalon-MM slave keeps the five largest values written to it, regardless of how many values are written. That way you can DMA a block of data to a single memory location, and then go and read the five greatest values.
Cheers,
Dave
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Hi thank you for your reply,
I synthetize my design through quartus II, and on the SOPC builder i add a new component and i call my HDL design. After this he appear to me the next window witch i will relate the signal of my design to tha avalon interface. I am not sur about the link that i make because it appear to me some warning.
My design have 16 input value coding in 16 bits. In reality it come from the RAM through the Nios II processor. If it is possible to relate my design directly with RAM it will be very good, beacuse i don't have any idea that's possible or no.
On my application i need to get the five greatest value of the first 16 memory value. Every time i will make the same think but on the next 16 value. I hope that it is clear.
Actually i just sysnthetize my design and i'am blocked on this step. How should i connect the input to the vavlon, because as i mentionned above, i am not sur about the link that i make this is first.
Second after i connect my custom instruction to the niosII, how i know the adress of every input and output.
Thank you
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