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I try to implement a VHDL code as custom user HDL. The component that i need to release is an algorithme that determine the five greatest value for 16 input in one clock cycle. I compile this project with modelsim it wok fine and i synthesize it through quartus II.
Now i try to integrate it with my design through SOPC builder.
I add it as a new component as illustrate on the attached file. My question is how can i acces to each input or output for my design.
For example i need to write a value on input 0. And read this value on max1 output.
Please help me.:(
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Have you actually designed this component as an SOPC Component? i.e., does it have an Avalon-MM slave interface to write the values and then enable the calculation of the five largest values.
What is the point of this algorithm?
How many bits do each value have? Where do these samples come from?
Rather than calculate the five highest values, I think keeping the five highest values are you write would be more efficient, i.e., the Avalon-MM slave keeps the five largest values written to it, regardless of how many values are written. That way you can DMA a block of data to a single memory location, and then go and read the five greatest values.
Cheers,
Dave
Honored Contributor
