query on avalan slave interface specification

HI All,

iam looking at the document of avalan mm slave interface specification.i am interested in interface level protocol with timings with respect to clock.

i have attached the timing diagram of read followed by write using wait_request here that i took from the document.

i am seeing once read got deasserted there is one clock cycle delay for the next write to be asserted.

i would like to know if read deassertion and write assertion can happen at the same clock edge?

in my case i see when read signal deassertion and write signal assertion ,if happens at the same clock edge,the slave code is getting stuck.

However the code works fine if i add some delay between two transactions.,

Regards,

Jagadish