Quartus thinks reset signal is a clock signal

Question

Hello,

My device is a 5M1270ZT144C4 and I am using Quartus Prime Version 22.1std 2 Build 922 07/20/2023 SC Lite Edition.

I am having a similar issue as the post https://community.intel.com/t5/Intel-Quartus-Prime-Software/Diagnosing-quot-signal-was-determined-to-be-a-clock-quot-message/m-p/22206#M4702.

The Timing Analysis shows the Reset signal as a clock signal.

None of the pins are defined and all of the logic is defined on diagrams (i.e. no VHDL/Verilog code). The reset signal does not go to the clock inputs of any logic. The image below shows the Clock signal (CLK1) and the Reset Signal (CPURST_25).

What can I do to fix this issue.

Stephen

_ak6dn_ · Answer

The one image you provide is completely insufficient to provide solution(s) to your problem.

You need to provide either the code or schematic connections of the RESET line to understand why you think Quartus thinks it is a clock.

The RESET line will appear in the timing analysis, as there is a timing associated with the RESET to DATAOUT arc in a cell.

That does not mean Quartus thinks RESET is a clock, only that their is a timing dependency on DATAOUT from RESET.

So long story short you need to provide a lot more documentation on your design.

sth125 · Answer

This code is for the company I work for, so I won't be able to supply you will all the logic diagrams.

I think I might have fixed it by right clicking on the signal in the the timing analyzers clocks window and selecting "remove clock". That will remove it from the sdc constraints file.

Do you think that is the fix or is it just covering up the issue.

sstrell · Answer

As mentioned, without more detail on the design or seeing the .sdc file, there's no way to tell if this is a valid fix.

nurina · Answer

Hello,I need more details and information to investigate your problem.Is it possible for you to share the .qar file of your project through email?I'm dropping you an email so you can send me your design through there.To generate a .qar file, go to Project&gt;Archive Project.Regards,Nurina

nurina · Answer

Hi,Can you provide some update?I have dropped you an email so that you can share your design there, please search for email subject "Intel Customer Support - Case #: 06034432"Regards,Nurina

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Quartus thinks reset signal is a clock signal

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