New Contributor
Frequent ContributorThe one image you provide is completely insufficient to provide solution(s) to your problem.
You need to provide either the code or schematic connections of the RESET line to understand why you think Quartus thinks it is a clock.
The RESET line will appear in the timing analysis, as there is a timing associated with the RESET to DATAOUT arc in a cell.
That does not mean Quartus thinks RESET is a clock, only that their is a timing dependency on DATAOUT from RESET.
So long story short you need to provide a lot more documentation on your design.
New ContributorThis code is for the company I work for, so I won't be able to supply you will all the logic diagrams.
I think I might have fixed it by right clicking on the signal in the the timing analyzers clocks window and selecting "remove clock". That will remove it from the sdc constraints file.
Do you think that is the fix or is it just covering up the issue.
