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I keep getting the error:
Error (10327): VHDL error at week7.vhd(23): can't determine definition of operator ""+"" -- found 0 possible definitions
and also this:
Error (10327): VHDL error at week7.vhd(21): can't determine definition of operator ""-"" -- found 0 possible definitions
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VHDL is looking for the operators '+' and '-' defined for std_logic_vector. However, that makes no sense, since the type std_logic_vector is just "vector of a bunch of bits". If you want the compiler to understand those bits mean numbers, then you need to use signed or unsigned to tell it which type of numbers you want.
Try the following:
library ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.all;
entity week7 is
port (A, B: in std_logic_vector(0 to 3); --this gives me 2 inputs that are 4 bits
S : out std_logic_vector(0 to 4); -- this is the 5 bit result
F : in std_logic_vector(0 to 2)); --this is the 3 bit function select
end week7;
architecture behavior of week7 is
-- Create some signed aliases
alias s_A is signed(A);
alias s_B is signed(B);
begin
process(A, B, F)
begin
if F = "000" then
S <= A;
elsif F = "001" then
S <= std_logic_vector(3 - resize(s_A,5));
elsif F = "010" then
S <= std_logic_vector(resize(s_A,5) + resize(s_B,5));
elsif F= "011" then
S <= std_logic_vector(resize(s_A,5) - resize(s_B,5));
elsif F = "100" then
S <= B;
elsif F = "101" then
S <= std_logic_vector(3 - resize(s_B,5));
elsif F = "110" then
S <= std_logic_vector(resize(s_A,5) + 1);
elsif F = "111" then
S <= std_logic_vector(resize(s_A,5) - 1);
end if;
end process;
end behavior;
The aliases s_A and s_B save having to put casts into the code. The resize(s_A,5) and resize(s_B,5) force the inputs to be sign-extended before being added or subtracted, with the result being assigned to S (after conversion to std_logic_vector).
I just typed this into the forum, so you may have to fix syntax errors. But this will get you on the right track.
If A, B, and S are always signed values in your design, then you should probably define them as such at the entity level.
Cheers,
Dave
Honored Contributor
