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student8's avatar
student8
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2 years ago

Quartus fails at the Fitter stage, with the following error message. How should I resolve this?"

Error (170143): Final fitting attempt was unsuccessful Info (170138): Failed to route the following 2 signal(s) Info (170139): Signal "tic:tic4|WideOr4~0" Info (170139): Signal "tic:tic6|stop_delt...
Configuration
Programmable Logic Device
TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

You can check whether the clock frequency in your design is relatively high, and whether there are signals with large fan-out and large data bit widths. These factors can lead to concentrated routing


  • student8's avatar
    student8
    Icon for New Contributor rankNew Contributor
    2 years ago

    Thank you for your reply.

    My data has a maximum bit width of 40 bits. I am not sure if this is considered wide data. Moreover, from the fitter report, there are no large fan-outs except for the clock signal. If there is a way to view all fan-out situations from other locations, please let me know.