Quartus doesnt recognize my FSM as a FSM

I changed to a one process FSM and i didnt got recognized also

process (reset_n, sysclk) is
  begin
    if reset_n = '0' then
      state_core      <= WAIT_START_CALC;
      mean_reg        <= (others => '0');
      first_time_reg  <= '1';
      aux_a_reg       <= (others => '0');
      contador_ph     <= 0;
      mag_out_reg     <= (others => '0');
      finish_calc_reg <= '0';
      read_counter    <= 0;
    elsif rising_edge(sysclk) then
      
    case state_core is
      
      when WAIT_START_CALC =>
        if start_calc = '1' then
          first_time_reg <= '1';
          if contador_ph = 31 then
            contador_ph <= 0;
            state_core  <= READY;
          else
            contador_ph <= contador_ph + 1;
          end if;
        end if;
        
      when READY =>
        finish_calc_reg <= '0';
        if first_time_reg = '1' then
          first_time_reg <= '0';
          state_core <= SUM_P1;
        else
          first_time_reg <= '0';
          if start_calc = '1' then
            if contador_ph = 31 then
              contador_ph <= 0;
            else
              contador_ph <= contador_ph + 1;
            end if;
            state_core <= SUM_P1;
          end if;
        end if;
        
      when SUM_P1 =>
        mean_reg   <= "00000" & memory_mean(read_counter);
        state_core <= SUM_P2;
        
      when SUM_P2 =>
        aux_a_reg <= aux_a_reg + mean_reg;
        if read_counter = 31 then
          state_core <= DONE;
        else
          read_counter <= read_counter + 1;
          state_core   <= SUM_P1;
        end if;
        
        
      when DONE =>
        mag_out_reg      <= aux_a_reg(20 downto 5);
        read_counter <= 0;
        finish_calc_reg  <= '1';
        aux_a_reg        <= (others => '0');
        state_core   <= READY;
        
        
      when others =>
        state_core <= WAIT_START_CALC;
    end case;
    end if;
  end process;