Qsys rename

Hi,

I am building a NiosII system with Qsys. Qsys makes a complete mess with the naming of the connections to the outside of the system.

Some are labelled as the were in SOPC Builder (.out_port_from_the_GPO()).

Another one is labelled as clk_100 (going to clk_in of clock source named clk_100)

The next one is labelled as clkin_240_clk (going to clk_in of second clock source named clk_240)

The sram pins seem to be <modulename>_<conduitname>_<signalname>_out

And finally the reset_n is just plain wrong, as it expects a positive logic reset signal (on toplevel: .reset_n(!reset_n))

    cpu u0 (
        .out_port_from_the_GPO(),
        .reset_n(),                              
        .clk_100(),
        .clkin_240_clk(),
        .sram_tcm_address_out(),
        .sram_tcm_byteenable_n_out(),            
        .sram_tcm_read_n_out(),                  
        .sram_tcm_write_n_out(),                
        .sram_tcm_data_out(),                    
        .sram_tcm_chipselect_n_out()            
    );

How can I change this pin naming? Preferrably to names I want to have, if not possible at least correct and consistent?

Cheers,

Andy