Qsys, Megawizard: HPC II DDR Memory Controller has different address width, WHY?

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Hi everyone,

for a DDR Memory device with bank addr 2 bits, row addr 13 bits and col addr 9 bits I generated a half rate hpc ii ddr memory controller using 2 methods: Megawiz and Qsys.

1. Megawiz: generated IP component has address width of 22 bits, which is expected as described in "emi.pdf"
   For one chip select: width = row bits + bank bits + column bits – 2 = 2 + 13 + 9 - 2 = 22

2. Qsys: generated IP component used in the Qsys sytem has address width of 25 bits, this is what I do not understand.

Could you please explain me what the 25 bits consist of?

Many thanks in forward.

Kind regards,

Hanel

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I finally found the answer myself. Also I forgot some important information in my question above:

• DDR memory device data width: 16 bit

• therefore Altera Half rate DDR controller (HPCII) local_wdata and local_rdata width: 64 bit

• HPCII address ordering: CHIP-BANK-ROW-COL

So when the DDR controller is generated by Mega wizard, the local address is word address (one word = 64bit = 8bytes).

• word address width = 2 bank bits + 20 bits (row bits + col bits - 2),
  minus 2 because HPCII word address range = DDR memory address range >> 2

But if the DDR controller is generated by Qsys, connected to the Avalon Memory Mapped bus, the address is byte address. The most 2 MSB bits are the bank bits.

• byte address width = 2 bank bits + 23 bits ((row bits + col bits - 2) + 3), plus 3 because in this case the byte address range = 8 * word address range = word address range << 3

Hope this will help some of you confronting this situation.

Have a nice day!

Hanel