Qsys fails (Error: ALTERA_HW_TCL_KEEP_TEMP_FILES)

Hi all! When i try to open my project in Qsys, i get errors:

Error: System.: set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
Error: System.: Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:/projects/fpga/2.5/hw/mcu/ip/alignment_pad_inserter/alignment_pad_inserter.v --source=D:/projects/fpga/2.5/hw/mcu/ip/alignment_pad_inserter/alignment_pad_inserter.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/Pavel/AppData/Local/Temp/alt6295_4622050850348362792.dir/0001_sopcqmap/
Error: System.: 
Error: System.: Command took 0.158s
Error: System.: Analyser output file not present: alignment_pad_inserter.v.xml
Error: System.: No definition of alignment_pad_inserter in D:/projects/fpga/2.5/hw/mcu/ip/alignment_pad_inserter/alignment_pad_inserter.v
Error: System.: set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
Error: System.: Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:/projects/fpga/2.5/hw/mcu/ip/ethernet_packet_multiplexer/ethernet_packet_multiplexer.v --source=D:/projects/fpga/2.5/hw/mcu/ip/ethernet_packet_multiplexer/ethernet_packet_multiplexer.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/Pavel/AppData/Local/Temp/alt6295_4622050850348362792.dir/0002_sopcqmap/
Error: System.: 
Error: System.: Command took 0.144s
Error: System.: Analyser output file not present: ethernet_packet_multiplexer.v.xml
Error: System.: No definition of ethernet_packet_multiplexer in D:/projects/fpga/2.5/hw/mcu/ip/ethernet_packet_multiplexer/ethernet_packet_multiplexer.v
Error: System.: set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
Error: System.: Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:/projects/fpga/2.5/hw/mcu/ip/udp_payload_inserter/udp_payload_inserter.v --source=D:/projects/fpga/2.5/hw/mcu/ip/udp_payload_inserter/udp_payload_inserter.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/Pavel/AppData/Local/Temp/alt6295_4622050850348362792.dir/0003_sopcqmap/
Error: System.: 
Error: System.: Command took 0.142s
Error: System.: Analyser output file not present: udp_payload_inserter.v.xml
Error: System.: No definition of udp_payload_inserter in D:/projects/fpga/2.5/hw/mcu/ip/udp_payload_inserter/udp_payload_inserter.v
Error: System.udpgen: TOP_LEVEL_MODULE not specified, file D:/projects/fpga/2.5/hw/mcu/ip/udpgen/udpgen.v contained multiple modules
Error: System.: set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
Error: System.: Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:/projects/fpga/2.5/hw/mcu/ip/ramka_bridge/ramka_bridge.v --source=D:/projects/fpga/2.5/hw/mcu/ip/ramka_bridge/ramka_bridge.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/Pavel/AppData/Local/Temp/alt6295_4622050850348362792.dir/0005_sopcqmap/
Error: System.: 
Error: System.: Command took 0.132s
Error: System.: Analyser output file not present: ramka_bridge.v.xml
Error: System.: No definition of ramka_bridge in D:/projects/fpga/2.5/hw/mcu/ip/ramka_bridge/ramka_bridge.v

Project that i try to open is worked - i use it some months earlier and then no make any changes within. I just try to open project again. P.S.: OS Win7x64, QII11sp2. Can anybody help me? Thanks!

UPD: This errors appears for custom cores only.