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Altera_Forum
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14 years ago

QSYS and JTAG Debugger

I have a design I've built in QSYS using a 16-bit bus. I'd like to include the JTAG to Avalon Master in my design so that I can do a quick system-level check using TCL commands before handing it off ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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That's puzzling, b/c QSYS gives the following error message

"Signal master[8] and signal avalon_slave_0[16] must have the same symbol width"

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That sounds like a how many bits per byte issue. Look in the _hw.tcl file for your component and see if you have a 16-bit symbol size, rather than 8-bit symbol size.

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I guess I could make the system 32-bit, but I'd prefer to figure out what's going on here. I thought that the bus width was automatically handled under QSYS.

I'm just using QSYS to connect the bus fabric and for the JTAG debug capability. The FPGA attaches externally to a separate DSP.

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The JTAG-to-Avalon-MM master, and SignaTap II are very useful for debugging problems, so its definitely worth figuring out what is wrong.

Cheers,

Dave