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mfbm's avatar
mfbm
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18 days ago

QSPI DDR Interface with Cyclone10LP: Maximum frequency

Hello, We are planning to implement a QSPI interface between Altera Cyclone10LP (10CL025YU256A7G) and a microcontroller iMXRT1180. The microcontroller is capable of a maximum frequency of 166 MHz (w...
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mfbm's avatar
mfbm
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15 days ago

Thank you very much for your answer and your suggestions. I see the general proposal is to use 1,8V LVCMOS standard on the pins. How much does it penalize using 3V3 LVCMOS standard vs. 1,8V in terms of achiveable frequency?

AdzimZM_Altera's avatar
AdzimZM_Altera
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13 days ago

Hi mfbm ,

 

"How much does it penalize using 3V3 LVCMOS standard vs. 1,8V in terms of achiveable frequency?"

  • Lower voltage I/O standards (e.g., 1.8V LVCMOS) support higher switching frequencies than higher voltage standards (e.g., 3.3V LVCMOS).
  • This is due to faster rise and fall times and reduced capacitive charging time at lower voltages.

 

Regards,

Adzim

  • mfbm's avatar
    mfbm
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    9 days ago

    Thank you for the answer. 

    But I still don't understand the benefit of using 1,8V LVCMOS if, according to the datasheet, the maximum Altera is guaranteeing is 200 MHz for both standards: "I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with a 10 pF load." Maybe 1,8V standard would support higher frequencies but if this is still not guaranteed by the manufacturer, the limit is still 200 MHz.

    Regards,

    Mabel

    • AdzimZM_Altera's avatar
      AdzimZM_Altera
      Icon for Regular Contributor rankRegular Contributor
      5 days ago

      Hi Mabel,

       

      Let's use 200MHz as the limit since it has been mentioned in datasheet.

      I think if using higher frequency, there might be some difficulty to meet timing.

       

      Regards,

      Adzim