Q on Avalon Tristate Slave Timing

Hi,

I've got a LAN chip which requires 13nS of nCS and/or nRD de-assertion time at the end of a read cycle. My NIOS is running at 100MHz, so I need 2 cycles of read hold. Unfortunately, hold time only applies to write cycles (according to the Avalon spec - and I have confirmed this on a scope).

So, the question is, is it OK to transfer this to the set-up time parameter (in the Avalon Tristate Slave Timing dialogue)? i.e. will this have the same desired effect - I think it will, but I'm not 100% sure that I won't get caught out somehow.

Regards,

D.