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Altera_Forum's avatar
Altera_Forum
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17 years ago

PWM signal problem

Hello,

could someone explain a strange problem with PW signal. The signal period is 30 ms, and PW triggers in between 0.7 and 2,2 ms.

But, I'v got a problem since the moment the signal rise it falls down again just like in the following picture.

http://img396.imageshack.us/img396/7549/pulse.png

I wonder if I have to assign special characteristics to the output pin in Quartus pin assignment sheet. I think VHDL code is ok. Perhaps some silly thing I overlooked.

18 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Daixiwen, definitely is not VHDL code. I tried different pins like 41, 144 but the same result. Is good to know that variables causes non-deterministic behaviour - elegant explanation.

    batfink, I checked the soldering, it is Ok. Normally, I use signals, but this is just a desparate try of using something different when ran out of idea what is wrong.

    Now I wonder if Cyclone II - EP2CST144C8 needs special configuration in Quartus. Looks like it can't make low frequency pulses in my case.

    Also how come that I'v got fmax lot higher then what was requested in the configuration. Say may physical clock runs at 25 Mhz, but I see actuall fmax 180.28 Mhz in Timing Analyser.
  • Altera_Forum's avatar
    Altera_Forum
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    I agree with Daixiwen - check the solder joints or try another pin.

    On the subject of shared variables, in Modelsim it comes up with a warning if you don't declare them as a protected type - this prevents the ":=" assignment and you can only use operations that you define - the protection makes these operations atomic. Actually I'm quite surprised that Quartus will let you synthesise shared variables at all.

    In this instance because one process assigns and the other reads PulseCounter, your code is safe-ish - without really thinking about it hard I couldn't say for sure if you might get a one clock cycle error depending on which process the simulator runs through on the clk edge - i.e. a one clock cycle discrepency between synthesis and simulation.

    Basically - like Daixiwen suggests - use a signal: this will get rid of all your issues there. Shared variables can be useful but I've only ever found them to be in certain circumstances in testbenches and system modelling. Signals are all you need for synthesis (although normal (i.e. not shared) variables can be useful on occassions but you don't really need them and you have to be careful if you use them).
  • Altera_Forum's avatar
    Altera_Forum
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    By the way why are you using a shared variable? It isn't recommended because of its non-deterministic behaviour. You have no way of forcing the execution order of your two processes. You should either merge the two processes, or use a signal.

  • Altera_Forum's avatar
    Altera_Forum
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    I don't think tit comes from the VHDL code, it's most likely a hardware problem.

    Is the pin soldered correctly? Can you map the signal to another pin and see if you have the same problem?
  • Altera_Forum's avatar
    Altera_Forum
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    batfink, he result is identical in either AC or DC couplings.

    I also created short VHDL code that behaves similar to above.

    
      -- every 3.84 uS - short pulse generates clock Tick 
      process (Clk)
      begin
      if (rising_edge(Clk)) then
           ClkCount <= ClkCount+1;
           if (ClkCount = 96) then     
         ClkTick <='1';
         ClkCount <= (others =>'0');
        else
         ClkTick <='0';
           end if;
       end if;
      end process;
     
      -- resets PulseCounter at 30 ms 
      -- PulseCounter is 13 bits long shared variable
      process (Clk,ClkTick)
      begin
       if (rising_edge(Clk)) then
        if(ClkTick ='1') then 
           PulseCounter := PulseCounter+1;
           if (PulseCounter = PulsePeriodRes) then
        PulseCounter := (others =>'0');
      end if;
      end if;
      end if;
      end process;
     
     -- Rxd_data is the compare value 
      process (Clk)
      begin
       if (rising_edge(Clk)) then
        if(PulseCounter<  Rxd_data) then
         Pwm_out<='1';
        else
         Pwm_out<='0';
        end if; 
       end if;
      end process;
    
  • Altera_Forum's avatar
    Altera_Forum
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    Daixiwen, some sort of input capacitance was my first impression too.

    I am using a probe with 18-35 pF compensation and I connected it straight to the output pin, nothing else is connected on it.
  • Altera_Forum's avatar
    Altera_Forum
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    Looks like you have a capacitor in series with your signal. Are you sure you are using the correct oscilloscope probe, in DC mode? What's connected to your pin?