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Devin2's avatar
Devin2
Icon for New Contributor rankNew Contributor
2 years ago

PWM outputs spike on startup of MAX10

I am using the PWM outputs on a MAX10 FPGA (the 10M50SAE144C8G) as triggers for the gate drivers in my H bridge circuit. I'm finding that on initial powerup of the circuit before my software starts r...
Configuration
Generic Io
Programmable Logic Device
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
FPGA pins are connected to weak pull-up resistors during power-on reset until the user mode configuration is active. The only way to avoid unwanted high level is to connect pull-down resistors. Minimal pull-up value for 3.3V VCCIO is 7k according to datasheet, you can calculate appropriate pull-down resistor value according to maximal logic low level of connected device.

1 - 2.2k should work in most cases.