Honored ContributorThere are several pulse signals will be input into FPGA through normal I/O pins. These pulse signals are generated with fast rising edge. My question is what effect will be when they go into fpga through normal I/O pins? Will the rising edge become slower? And how to ensure their primary property without any change?
Honored ContributorA 'fast rising edge' won't affect the ability of the FPGA to put the signal to use internally. As long as the signal you're driving into the FPGA complies with the input voltage limits of your chosen device, you won't have any problems.
Once inside the FPGA the edge speed will not necessarily resemble the edge speed of the input signal. If this is what you consider a 'primary property' then no, you cannot guarantee that the signal's edge speed won't change. Whether fed onto a clock domain or into logic, the edge speed will be a function of the internal fabric and not your input signal. If you chose to feed that same signal directly out of another FPGA pin then again, the edge speed will be dependant on factors other than the input signal's edge speed. The output buffer's drive strength and pin loading (the circuitry the pin is driving) will dominate the edge speed you can achieve. Regards, AlexHonored Contributorwhat kind of speeds are you talking about?
