pulse generation

Could you clarify? Do you need a produce a pulse of a fixed length or pulses of varying length. For example, does it need to sweep from 2.5 to 3.5ns or can it simply consistently generate say a 3.0ns pulse?

This violates all kinds of rules and normally I would never do this but here's a shot:

module edge_detect(
    input   clk_150,
    input   edge_in,
    output  edge_pulse
);
reg    edge_in_r;
assign      edge_pulse = clk_150 & ^edge_in_r;
always @(posedge clk_150)
    edge_in_r   <= {edge_in_r,edge_in};
endmodule

In bdf designs, LOGIGCELL symbols can be used to define delays, that are kept during synthesis. You can try with around ten logic cells.

to jakobjones (http://www.alteraforum.com/forum/member.php?u=2226), thanks yes I am trying to produce a single pulse and one at 3nS would be perfect. I have been using the solution that FvM suggests with logic cells in the delay path from input pin and other path direct to logic. I was trying to defeat the optimizer from balancing the 2 paths for a little more control.

Without setting additional timing constraints, no balancing would occur.