Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorpulse generation
Hello Forum, I have an application that requires me to produce 2.5 - 3.5nS pulses from externally generated edges. Our target device is a Cyclone 1C6 and SW Quartus 7.2. In the IOE descript...
Altera_ForumHonored Contributor
Honored ContributorIn bdf designs, LOGIGCELL symbols can be used to define delays, that are kept during synthesis. You can try with around ten logic cells.
