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Altera_Forum's avatar
Altera_Forum
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14 years ago

'Pseudo-Differential I/O' Error

I'm currently designing a DDR2 controller and have gotten far enough that I'd like to implement the design and check my work. I threw it into Quartus II 9.1 and have been getting the following error concerning the pin layout.

Error: Pin "DDR2_DQS[1]" has a pseudo-differential I/O standard but does not have its complement pin. Because the output enable of the buffer is in use, the Fitter will not create a negative pin without a complement output enable path.

I generate the DDR2_DQS signal, and it is my understanding that Quartus will automatically come up with its partner (which seems to have been named DDR2_DQS[1](n) ).

Does anyone have any idea how to get around this problem? I've tried multiple solutions to no avail. I'm currently trying to generate both parts of the differential using a bi-direction pseudo-differential buffer megawizard, but I don't believe that will work either.

Any advice would be great!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Altera's DDR3 core has explicit dqs and dqs_n pins. my guess is that the reason is mentioned in the error, "Because the output enable of the buffer is in use, the Fitter will not create a negative pin without a complement output enable path."

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    your best best is probably to generate an Altera DDR2 core and trace the dsq and dqs_n pins back to their driver. the PHY is clear text, so you'll be able to read the RTL