Properly Constraining Inverted Clock with TimeQuest

1. Create a RX_PCLK base clock with

create_clock -name RX_PCLKC -period ... [get_ports RX_PCLK]

2. Create a RX_PCLK_virt virtual clock with (create clock)

create_clock -name RX_PCLKC_virt -period ...

3. Set your input delay constraints using RX_PCLK_virt and -clockfall

set_input_delay -min ... -clock RX_PCLK_virt -clockfall [get_ports ... ]

set_input_delay -max ... -clock RX_PCLK_virt -clockfall [get_ports .... ]

4. Create a TX_PCLK derived clock that is the same as TX_PCLK

create_generated_clock -name TX_PCLK -source [get_ports RX_PCLK] [get_posts TX_PCLK]

5. Set your output delays relative to TX_PCLK using -clockfall

set_output_delay -min ... -clock TX_PCLK -clockfall [get_ports ... ]

set_output_delay -max ... -clock TX_PCLK -clockfall [get_ports .... ]

6. Create a generated inverted pixel_clock.

create_generated_clock -name pixel_clock -source [get_ports RX_PCLK] -invert [get_nets pixel_clock]

However, I think Quartus will recognize this during synthesis and convert all the posedge logic fed by pixel_clock to negedge logic.

If it does this, this create_generated_clock is problably unecessary and will problably fail as well.