Programming EPCQ from External processor

Question

Hi,
We are targeting Arria 10 GX &amp; we want to use 3 EPCQ devices to contain 3 different Binaries controlled by nCSO [0:2] lines in the custome hardware design.
Also, in the custom hardware, there is an NVIDIA processor is present. In the product version we want to update the EPCQ content from the processor instead of updating the EPCQ content (jic) over JTAG.
We came to know that there is an IP called  " remote update IP" and that could be used for updating EPCQ. However I am not clear with regards to the interface between Processor &amp; FPGA. Is it possible to update over SPI or PCIe interface from External processor?
I have attached the system level block diagram for your reference.
With Regards,
HPB

johnt_altera · Answer

Hi,The remote update IP is only use to remotely reconfigure the FPGA with the new bitstream. It cannot be use to update the EPCQ device.You use any interface connected to the FPGA where the interface IP need to communicate with the Generic Serial Flash Interface IP (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf) in order to update the EPCQ flash.

hbhat2 · Answer

Hi,

Thanks for the reply. With respect to using "Generic Serial Flash Interface IP", I have couple of questions.
1) Do you have any source code / reference design  to interface the External processor to JTAG UART module of FPGA?
2) We are not  planning to use Quartus programmer or any Intel tools from Host PC to update the EPCQ device. Is it possible to update without Quartus programmer or Nios console to interface between External processor &amp; FPGA .

With Regards,
HPB

johnt_altera · Answer

Hi,You can refer to https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/generic-serial-flash-interface-intel-fpga-ip-core-reference-design/ which is  a reference design for Cyclone V E. You can migrate the design to Arria 10.

hbhat2 · Answer

Hi,
Thanks for the quick reply. I downloaded &amp; understood the example design on high level.
I understood that the host interface is through JTAG. 
As I mentioned previously, we are connecting the FPGA to external processor without JTAG. So, we do not want any dependency of tools like USB blaster/Quartus programmer/Nios Console.
This requirement is for the field upgradable option of Arria 10 based product. 
Our requirement is the external processor must have a standard interface like UART/SPI and the external processor must be able to send the new Flash content through SPI/UART to FPGA. The FPGA must then send those contents to EPCQ flash.
To support above requirement, flash interface IP is fine in the flash side. But, the way FPGA receives the flash content through JTAG is the concern. 
How to send the JIC content from External processor to FPGA over UART/SPI?
What file format of JIC content must be sent by the external processor to FPGA?
With Regards,
HPB

johnt_altera · Answer

Hi,I would recommend you to send rpd file rather than jic file. You can modify the design example to UART or other interface. You can also refer to https://fpgacloud.intel.com/devstore/platform/15.1.0/Standard/remote-system-upgrade-over-uart-based-on-nios-ii-processor-with-epcq/ which performed remote update and you can add the Generic Serial Flash IP in order to update the flash content.

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Programming EPCQ from External processor

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