Contributor
Regular ContributorHi,
You can refer to https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/generic-serial-flash-interface-intel-fpga-ip-core-reference-design/ which is a reference design for Cyclone V E. You can migrate the design to Arria 10.
ContributorHi,
Thanks for the quick reply. I downloaded & understood the example design on high level.
I understood that the host interface is through JTAG.
As I mentioned previously, we are connecting the FPGA to external processor without JTAG. So, we do not want any dependency of tools like USB blaster/Quartus programmer/Nios Console.
This requirement is for the field upgradable option of Arria 10 based product.
Our requirement is the external processor must have a standard interface like UART/SPI and the external processor must be able to send the new Flash content through SPI/UART to FPGA. The FPGA must then send those contents to EPCQ flash.
To support above requirement, flash interface IP is fine in the flash side. But, the way FPGA receives the flash content through JTAG is the concern.
How to send the JIC content from External processor to FPGA over UART/SPI?
What file format of JIC content must be sent by the external processor to FPGA?
With Regards,
HPB
