Programming Cyclone III (EP3C16Q240C8N) on ARM board

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My interest is to know if someone have try to install Quartus II programmer on a ARM linux and if it worked?

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Its not possible.

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My second interest is to see the source code that do that. I have not see the source code of Quartus II Programmer, is it available?

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No, its not available.

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My last question is if anybody have any suggestion of open source project that could do the programmation of cyclone III using USB blaster or JTAG?

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If you have the USB-Blaster connected to the USB port on the ARM processor, and that ARM processor is running Linux, then you can look at the USBIP project:

http://usbip.sourceforge.net/

I tested the following configuration; Freescale PowerPC QorIQ P2020 COM Express running Linux, with the BeMicro-SDK board plugged into the USB port (the board has an on-board USB-Blaster), and then ran USBIP server on that board. I had a USBIP client running on an Ubuntu 11.04 x86 64-bit laptop, and could program the BeMicro-SDK.

However, if you are designing an ARM board with an FPGA, you can just program the FPGA directly ...

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf)

But you would not have access to the SignalTapII logic analyzer, NIOS debugger, etc, using this latter method.

Cheers,

Dave

Not really sure what you need, but you might also be interested in a STAPL player. IIRC, there's some source code available for that.

http://www.altera.com/support/devices/tools/jam/tls-jam.html

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Its not possible.

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No, its not available.

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OK thx. Do they think of doing it? I mean the ARM port and maybe not the open source option?

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If you have the USB-Blaster connected to the USB port on the ARM processor, and that ARM processor is running Linux, then you can look at the USBIP project:

http://usbip.sourceforge.net/

I tested the following configuration; Freescale PowerPC QorIQ P2020 COM Express running Linux, with the BeMicro-SDK board plugged into the USB port (the board has an on-board USB-Blaster), and then ran USBIP server on that board. I had a USBIP client running on an Ubuntu 11.04 x86 64-bit laptop, and could program the BeMicro-SDK.

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That will not work with my setup since I'm having a ARM board + USB cable + [FX2 micro controller] + FPGA. I don't have a Fpga with nios and so I'm not able to use usbip. By the way I went to LinuxCon at Vancouvers and at the USB mini-summit they talk of a possible rewrite / replacement for the usbip : http://hansdegoede.livejournal.com/ Hans have made nice and interesting presentation on the subject and offer a interesting solution on the user space...

http://events.linuxfoundation.org/events/linuxcon/goede

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However, if you are designing an ARM board with an FPGA, you can just programming the FPGA directly ...

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf)

But you would not have access to the SignalTapII logic analyzer, NIOS debugger, etc, using this latter method.

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Thx for the link but that link discuss about PS & FPP why not using JTAG? What's the benefit of using these 2? any open source project using these technics?

I found this anyone have play with this?

http://sourceforge.net/projects/urjtag/

Best Regards,

kap

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OK thx. Do they think of doing it? I mean the ARM port and maybe not the open source option?

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Unlikely.

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That will not work with my setup since I'm having a ARM board + USB cable + [FX2 micro controller] + FPGA. I don't have a Fpga with nios and so I'm not able to use usbip.

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You misunderstand. USBIP would run on the ARM processor, and it allows the USB-Blaster USB connection to be accessed from another machine as a local USB port. This allows an x86 machine running Quartus to 'attach' to the USB port on your ARM processor. Quartus then sees the USB device as a locally attached USB-Blaster.

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By the way I went to LinuxCon at Vancouvers and at the USB mini-summit they talk of a possible rewrite / replacement for the usbip : http://hansdegoede.livejournal.com/ Hans have made nice and interesting presentation on the subject and offer a interesting solution on the user space...

http://events.linuxfoundation.org/events/linuxcon/goede

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Cool! Thanks for the links.

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Thx for the link but that link discuss about PS & FPP why not using JTAG? What's the benefit of using these 2?

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Because JTAG is slow (and so is PS). If you need an FPGA loaded fast, then FPP is the solution.

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any open source project using these technics?

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There is nothing really 'open-source' about PS and FPP. They just documented methods for configuring an FPGA.

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I found this anyone have play with this?

http://sourceforge.net/projects/urjtag/

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I haven't played with the UrJTAG tools. However, that is the site that has the most details on the USB-Blaster protocol. You can use that information to control your USB-Blaster from FTD2XX DLLs or libusb and libftdi.

However, even with that knowledge, you still cannot program your FPGA via JTAG, without the protocol for converting an .sof or .pof or .rbf file into a JTAG data stream. You could reverse engineer that using a logic analyzer though.

Cheers,

Dave

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However, even with that knowledge, you still cannot program your FPGA via JTAG, without the protocol for converting an .sof or .pof or .rbf file into a JTAG data stream. You could reverse engineer that using a logic analyzer though.

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You'll find part of the information documented with the Altera JRunner project.

Another option is to to take a detour way over JAM STAPL code.

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Not really sure what you need, but you might also be interested in a STAPL player. IIRC, there's some source code available for that.

http://www.altera.com/support/device...m/tls-jam.html

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Thx, What I want is a software that can be cross compile on a embedded computer running ARM processor connected by USB blaster OR JTAG to a FPGA that can help me program / flash the .jic, .soft file.

Hope that this is clarifying what I'm searching.

Best Regards

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You misunderstand. USBIP would run on the ARM processor, and it allows the USB-Blaster USB connection to be accessed from another machine as a local USB port. This allows an x86 machine running Quartus to 'attach' to the USB port on your ARM processor. Quartus then sees the USB device as a locally attached USB-Blaster.

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No I completely understand that part. Sorry if I'm not clear, I cannot use another computer or if you prefer we don't want ;) This is a question of maintenance. The embedded device running with the ARM processor should manage/update the software running on the FPGA.

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Because JTAG is slow (and so is PS). If you need an FPGA loaded fast, then FPP is the solution.

There is nothing really 'open-source' about PS and FPP. They just documented methods for configuring an FPGA.

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Thx for the clarification.

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I haven't played with the UrJTAG tools. However, that is the site that has the most details on the USB-Blaster protocol. You can use that information to control your USB-Blaster from FTD2XX DLLs or libusb and libftdi.

However, even with that knowledge, you still cannot program your FPGA via JTAG, without the protocol for converting an .sof or .pof or .rbf file into a JTAG data stream. You could reverse engineer that using a logic analyzer though.

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hmmmm....

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You'll find part of the information documented with the Altera JRunner project.

Another option is to to take a detour way over JAM STAPL code.

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https://www.altera.com/download/legacy/jrunner/dnl-jrunner.html?gsa_pos=2&wt.oss_r=1&wt.oss=jrunner#about

From what I'm reading about JRunner and JAM STAPL is could be possible to code or modify my own version.

thx will keep reading

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From what I'm reading about JRunner and JAM STAPL is could be possible to code or modify my own version.

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Porting the Jam player is pretty simple. I use it for programming EPC2 EEPROMs (used with FLEX10K FPGAs), and for programming MAX II CPLDs.

Porting the Jam player basically involves supplying toggle I/O routines for controlling the JTAG pins.

While this gives you the ability to (slowly) program the FPGA, it does not give you convenient access to the SignalTap II logic analyzer.

One way to look at your system design, is to consider what is needed for operation, and what is needed for debug. In my systems, I have generally used PS and FPP for configuration of the FPGAs, and then plugged a JTAG cable in when needing to debug. For example;

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)

However, for really tricky bugs that occur infrequently and randomly across multiple boards (eg., on one board out of 100+), plugging a JTAG cable into all of them is not an option. In the new system I am designing, I will have both a 'fast' programming method (FPP) and a debug method (eg., SignalTap II via JTAG). I also need a low- to medium-speed communications mechanism (for control commands) between the host and the FPGA. With these requirements in mind, I'm looking at using the FT2232H as both a USB-Blaster clone (so that Quartus recognizes it), and as a USB-to-parallel communications channel (20MB/s for the FT2232H in synchronous mode). I'm currently working on the documentation/test results now, I'll post it when its done.

Cheers,

Dave

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Porting the Jam player is pretty simple. I use it for programming EPC2 EEPROMs (used with FLEX10K FPGAs), and for programming MAX II CPLDs.

Porting the Jam player basically involves supplying toggle I/O routines for controlling the JTAG pins.

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I had more times to check the source code of JAM STAPL and compile it for UNIX. Since I need to port the code for embedded linux board with OMAP3. I configure the MUX pins of the ARM processor to associate to specific GPIO that I will use for TCK,TMS,TDI,TDO.

So now what I need to understand in the jbistub.c from JAM is why :

1- Before each read it does this write of 0x7E:

ch_data = 0x7e;

write(com_port, &ch_data, 1);

THIS mean that 01111110 and since

TCK = bit 0

TMS = bit 1

TDI = bit 6

TDO = bit 7

So TCK = 0, TMS = 1, TDI = 1 and TDO = 0

So why doing this before each read? Is it only specific to parallel port of JTAG specific?

From this document page 9

http://www.altera.com/literature/hb/max2/max2_mii51015.pdf

2- Second question why looping 100 for the read? parallel port specific or JTAG? Maybe a validation to simply be sure to read the value and not missing it because the read is done to fast??? That seem to me a poor way to code this?

for (i = 0; (i < 100) && (result != 1); ++i)

{

result = read(com_port, &ch_data, 1);

}

if (result == 1)

{

tdo = ch_data & 0x01;

}

else

{

fprintf(stderr, "Error: BitBlaster not responding\n");

}

Regards,

Kevyn-Alexandre Paré