RCSaiCharanNew Contributor5 years agoProgrammable IOE Delay: MAX10 Trying to set /change value of Input delay from pin to internal cell parameter for a clock input which is feeding to Altera GPIO Lite IP instance (set in ddr mode).However for different values of th...Show More
Recent DiscussionsLooking for the Document ID 854068SolvedAbout floating voltage of the Agilex 3 power on resetSuggestion of carry chain type TDC of Cyclone 10 GX FPGA chipsIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAImplementation of lower data rate.