Altera_Forum
Honored Contributor
Honored ContributorProgram counter with ripper adder in VHDL
no longer need help thnx:D
Forum Discussion
7 Replies
Altera_ForumI would start again, and think about making the design synchronous. Currently, with it being asynchronous, you are likely to run into all sorts of timing problems and it is unlikely to work very well, if at all.
Secondly, you have not written any functions. You have created entities. You cannot use an entity inside a process, you can only instantiate it in parrallel to processes. Communication between processes/entities is done via signals.- Altera_Forum
i didnt add entity inside a process, can you point out which one it is?
The add8 entity should be correct, i'm just confused how to use this ripper adder thing inside counter . - Altera_Forum
I dont understand the problem you have. What is wrong with what you have already written? (apart fromt the fact there is no "add_inc" port on the add8 entity).
- Altera_Forum
ye that was a mistake, i deleled somewhere else.
Ok for example, if pc_increment=1, so that we need to increase the counter by one, how do i use the add8 to do it? - Altera_Forum
If you synchronise the design, you can use pc_increment as the clock enable for the adder.
With the asynchronous circuit you have, you're rather stuck. - Altera_Forum
thank you for the advice. however, so far i've only thinked of a way doing like this:
if pc_increment' event and pc_increment='1' then give signal of current pc value to input of adder; then get sum from adder, link to pc value is that the way we do it? - Altera_Forum
No
What you are doing is turning pc_increment into a clock. What you are also describing is software. In VHDL, you dont pass values into an entity, and take the results and pass them to something else. You have to remember that all signals run in parrallel. Without a clock, there is no easy way to ensure that event A happens before event B. First thing - go back and learn about digital logic design. From what you have posted, you are clearly a software programmer with little knowledge of digital design. Learn how digital logic works before trying to write VHDL Second. Delete all your code and start again with a clock.
